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HI08
Table 2-9. Interrupt and Mode Control (Continued)
Signal Name
MODC
Type
Input
State During
Reset
Input,
Schmitt-trigger
Signal Description
Mode Select C —MODA, MODB, MODC, and MODD select one of
16 initia l chip operating modes, latched into the OMR when the
RESET signal is deasserted.
IRQC
Input
External Interrupt Request C —After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the processor
is in the WAIT standby state and IRQC is asserted, the processor
exits the WAIT state.
MODD
Input
Input,
Schmitt-trigger
Mode Select D —MODA, MODB, MODC, and MODD select one of
16 initia l chip operating modes, latched into the OMR when the
RESET signal is deasserted.
IRQD
Input
External Interrupt Request D —After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the processor
is in the WAIT standby state and IRQD is asserted, the processor
exits the WAIT state.
2.7 HI08
The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08
supports a variety of standard buses and can directly connect to a number of industry-standard
microcomputers, microprocessors, DSPs, and DMA hardware.
Table 2-10. Host Interface
Signal Name
H[0–7]
Type
Input/Output
State During
Reset 1, 2
Ignored Input
Signal Description
Host Data— When the HI08 is programmed to interface with a
non-multiplexed host bus and the HI function is selected, these signals are
lines 0–7 of the Data bus.
HAD[0–7]
PB[0–7]
Input/Output
Input or
Output
Host Address— When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, these signals are lines
0–7 of the Address/Data bus.
Port B 0–7— When the HI08 is configured as GPIO through the HPCR, these
signals are individually programmed through the HI08 Data Direction
Register (HDDR).
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
2-9
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